Audio digital signal processors typically receive data packets from a 32 bit PCI bus interface. These packets then must be delivered as a single contiguous byte stream to an 8-bit digital signal processor (DSP). The packets are not of fixed byte size and alignment, but instead may be of arbitrary (different) byte size and of different alignment (start byte and end byte address within a 32 bit double word). Data typically is routed through four 8-bit wide RAMs used as first in first out (FIFO) buffers. To accomplish the routing, the traditional implementation is to use a complete 32-bit to 32-bit switch, such that any incoming byte can be routed to any FIFO RAM. A typical design of such a system requires 32 four-to-one multiplexors, or sixteen 8-bit tristate buffers, plus additional control logic, to generate a contiguous 8-bit wide data stream supplied to the DSP data bus.
The steering logic required by the 32-bit to 32-bit switch requires a significant amount of silicon on the integrated circuit chip for the system. In addition, the data steering logic or control logic is somewhat complex.
It is desirable to simplify the circuit design of an audio digital signal processor by eliminating the 32-bit to 32-bit switch and the associated data steering logic.